With custom ICs for use in an ASIC (Application Specific Integrated Circuit) or the like, attempts have heretofore been taken to refine transistors to the lower a power supply voltage for thereby improving operating speeds. With these custom ICs, a variety of memory devices are embedded. A need also arises for these embedded memory devices to similarly operate at the high speed and low power supply voltages and, in application to, for instance, cash memories or the like, a static random access memory (SRAM: Static Random Access Memory that is herein after referred to as SRAM) similarly needs to operate at the high speed and low power supply voltages.
An SRAM of the related art is described with reference to FIG. 1. FIG. 1 shows a circuit structure of a unit cell (hereinafter referred to as an SRAM cell) of the related art SRAM by which a cache memory is structured. In a case where a word line signal WL lies a low voltage potential, forming two CMOS (Complementary Metal Oxide Semiconductor) inverters in loop connection enables data to be stably stored. That is, one of the CMOS inverts has an input formed of a data storage node V1 to allow inverted data of data stored in the node V1 to be output to a data storage node V2 and the other of the CMOS inverts has an input formed of a data storage node V2 to allow inverted data of data stored in the node V2 to be output to the data storage node V1.
However, in an event that the word line signal WL is accessed to be raised to a high voltage potential, the data storage nodes V1, V2 and bit line pair BLT, BLN are made conductive to each other via access transistors to cause the low voltage potential of the data storage nodes V1, V2 to be raised from a ground potential, resulting in a difficulty of stably holding data. In general, with the related art SRAM, a static noise margin (SNM: Static Noise Margin) has heretofore been used as an index for measuring a stability of data storage during access operation.
That is, a butterfly curve is drawn as shown in FIG. 2 when two DC (direct current) characteristics are overlapped each other with an SRAM formed of two separate inverters by which DC characteristics of the respective inverters are obtained to allow a DC characteristic output of one of the inverters to be a DC characteristic input of the other of the inverters. The SNM is defined as one side of a maximal square inscribed in the butterfly curve.
This SNM has been subjected to future prospects in Literature 1 (A. J. Bhavnagarwala “The impact of intrinsic device fluctuations on CMOS SRAM cell stability,” IEEE Journal of Solid State Circuit, Vol. 36, No. 4, April 2001 (FIG. 5, FIG. 10)). That is, a channel length of a used transistor is refined as shown in FIG. 3 and if the channel length of the transistor shifts from 250 nm to 50 nm, not only the SNM has a decreased average value but also a deviation in the SNM increases. Accordingly, remarkable deterioration occurs in a worst value of the SNM. With the channel length of a value of 50 nm as shown, the worst value of the SNM becomes a value less than “0” and, hence, stored data has a risk of being corrupted when read operation is executed and a word line signal goes to a high voltage potential.
In the meanwhile, Literature 2 (H. Sakakibara, “A 750 MHZ 144 Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST,” IEEE International Solid State Circuit Conference, 2003 (FIG. 1)) has proposed an SRAM with a read-only port. This SRAM includes a memory cell comprised of eight transistors wherein a bit line takes a full swing only with a cell current of a memory cell. An original object of this system is to obtain an operating speed improvement effect in case of advancing a generation. Furthermore, since no flow of electric charge occurs from the bit line to a data storage node inside a cell during the read operation, no probability occurs for stored data to be corrupted due to read operation in an issue encountered by the related art SRAM in a future. Consequently, the SRAM resulting from such a circuit configuration can perform not only a high-speed operation in an advanced generation but also stable operation.
As disclosed in Literature 1 stated above, with the related art SRAM using six transistors, deterioration occurs in the worst value of the SNM, causing a difficulty to occur in stable data storage as a future possibility. In this respect, reference is now made to FIGS. 5 and 6 in combination to describe a mechanism why corruption of stored data occurs during the read operation that would occur when the SNM has insufficient value.
With a conventional cell, as a word line signal WL is selected as shown in FIG. 6(A), a low voltage potential “0” of a data storage node merely increases from a ground potential to a slight extent as shown in FIG. 6(B) in case of a storage node of the conventional cell. However, fluctuation occurs in a threshold voltage of an NMOS (N-channel MOS) transistor forming an inverter adapted to be applied with that voltage potential and if a remarkable drop occurs in the threshold voltage, the NMOS transistor tends to be turned on and, hence, an output of the inverter drops from a high voltage potential “1”. This causes a voltage potential of the data storage node to be inverted as shown in FIG. 6(C), causing corruption of data to occur.
In the meanwhile, while no corruption of stored data caused by read operation takes place in the SRAM cell with the read-only port disclosed in Literature 2, an issue arises in a consequence of the eight transistors with the resultant need for five control signals as a whole causing an increase in a memory cell dimension.
The present invention has an issue to be addressed wherein even if ultra-high speed operation or ultra-low voltage operation are needed, a need arises to provide the eight transistors with a large number of control signals in order for structuring a memory cell operative to prevent corruption of stored data resulting from read operation and, therefore, a difficulty is encountered in reducing a memory cell dimension.